The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices
Two doping methods for introducing phosphorus atoms into polysilicon to form a gate electrode for 0.5 mm CMOS were investigated. These methods were ion implantation and the ”in-situ” one (it is also known as thermal diffusion). For the in-situ method, the concentration of 1.8.10²⁰cm-³ for Si₂H₆ and...
Gespeichert in:
| Datum: | 2002 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | English |
| Veröffentlicht: |
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
2002
|
| Schriftenreihe: | Semiconductor Physics Quantum Electronics & Optoelectronics |
| Online Zugang: | http://dspace.nbuv.gov.ua/handle/123456789/121185 |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Назва журналу: | Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| Zitieren: | The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices / I. Ahmad, A. Omar, A. Mikdad // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2002. — Т. 5, № 2. — С. 188-192. — Бібліогр.: 14 назв. — англ. |
Institution
Digital Library of Periodicals of National Academy of Sciences of Ukraine| id |
irk-123456789-121185 |
|---|---|
| record_format |
dspace |
| spelling |
irk-123456789-1211852017-06-14T03:06:32Z The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices Ahmad, I. Omar, A. Mikdad, A. Two doping methods for introducing phosphorus atoms into polysilicon to form a gate electrode for 0.5 mm CMOS were investigated. These methods were ion implantation and the ”in-situ” one (it is also known as thermal diffusion). For the in-situ method, the concentration of 1.8.10²⁰cm-³ for Si₂H₆ and phosphane (PH3) were used, in the course of ion implantation applying two different doses: 2.0.10¹⁶ and 3.10¹⁶cm-² at 40 keV. The micromorphology of the polysilicon surface was studied using the atomic force microscopy (AFM). The polysilicon thickness obtained via the in-situ method ranged between 12.35 and 26.08 nm, with an average value thickness of 18.0 nm, and its sheet resistance value was 21±1 ohm/square. As for the ion implantation method, at the lower doses the thickness ranged at about 12.00 upto 46.0 nm with an average value of 24.0 nm, and its sheet resistance values were of 36±13 and 45±21 ohm/square, respectively. At the higher doses, the thickness varied from 12.16 to 47.84 nm with an average meaning 23.96 nm, and its sheet resistance value was between 25 to 40 ohm/square. Therefore, polysilicon doped by the in-situ method has smoother and thinner surface and possesses better electrical properties. 2002 Article The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices / I. Ahmad, A. Omar, A. Mikdad // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2002. — Т. 5, № 2. — С. 188-192. — Бібліогр.: 14 назв. — англ. 1560-8034 http://dspace.nbuv.gov.ua/handle/123456789/121185 en Semiconductor Physics Quantum Electronics & Optoelectronics Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України |
| institution |
Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| collection |
DSpace DC |
| language |
English |
| description |
Two doping methods for introducing phosphorus atoms into polysilicon to form a gate electrode for 0.5 mm CMOS were investigated. These methods were ion implantation and the ”in-situ” one (it is also known as thermal diffusion). For the in-situ method, the concentration of 1.8.10²⁰cm-³ for Si₂H₆ and phosphane (PH3) were used, in the course of ion implantation applying two different doses: 2.0.10¹⁶ and 3.10¹⁶cm-² at 40 keV. The micromorphology of the polysilicon surface was studied using the atomic force microscopy (AFM). The polysilicon thickness obtained via the in-situ method ranged between 12.35 and 26.08 nm, with an average value thickness of 18.0 nm, and its sheet resistance value was 21±1 ohm/square. As for the ion implantation method, at the lower doses the thickness ranged at about 12.00 upto 46.0 nm with an average value of 24.0 nm, and its sheet resistance values were of 36±13 and 45±21 ohm/square, respectively. At the higher doses, the thickness varied from 12.16 to 47.84 nm with an average meaning 23.96 nm, and its sheet resistance value was between 25 to 40 ohm/square. Therefore, polysilicon doped by the in-situ method has smoother and thinner surface and possesses better electrical properties. |
| format |
Article |
| author |
Ahmad, I. Omar, A. Mikdad, A. |
| spellingShingle |
Ahmad, I. Omar, A. Mikdad, A. The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices Semiconductor Physics Quantum Electronics & Optoelectronics |
| author_facet |
Ahmad, I. Omar, A. Mikdad, A. |
| author_sort |
Ahmad, I. |
| title |
The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices |
| title_short |
The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices |
| title_full |
The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices |
| title_fullStr |
The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices |
| title_full_unstemmed |
The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices |
| title_sort |
effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron cmos devices |
| publisher |
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України |
| publishDate |
2002 |
| url |
http://dspace.nbuv.gov.ua/handle/123456789/121185 |
| citation_txt |
The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices / I. Ahmad, A. Omar, A. Mikdad // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2002. — Т. 5, № 2. — С. 188-192. — Бібліогр.: 14 назв. — англ. |
| series |
Semiconductor Physics Quantum Electronics & Optoelectronics |
| work_keys_str_mv |
AT ahmadi theeffectofdopingmethodsonelectricalpropertiesandmicromorphologyofpolysilicongateelectrodeinsubmicroncmosdevices AT omara theeffectofdopingmethodsonelectricalpropertiesandmicromorphologyofpolysilicongateelectrodeinsubmicroncmosdevices AT mikdada theeffectofdopingmethodsonelectricalpropertiesandmicromorphologyofpolysilicongateelectrodeinsubmicroncmosdevices AT ahmadi effectofdopingmethodsonelectricalpropertiesandmicromorphologyofpolysilicongateelectrodeinsubmicroncmosdevices AT omara effectofdopingmethodsonelectricalpropertiesandmicromorphologyofpolysilicongateelectrodeinsubmicroncmosdevices AT mikdada effectofdopingmethodsonelectricalpropertiesandmicromorphologyofpolysilicongateelectrodeinsubmicroncmosdevices |
| first_indexed |
2025-07-08T19:21:39Z |
| last_indexed |
2025-07-08T19:21:39Z |
| _version_ |
1837107774450827264 |
| fulltext |
Semiconductor Physics, Quantum Electronics & Optoelectronics. 2002. V. 5, N 2. P. 188-192.
© 2002, Institute of Semiconductor Physics, National Academy of Sciences of Ukraine188
PACS:
The effect of doping methods on electrical properties and
micromorphology of polysilicon gate electrode
in submicron CMOS devices
I. Ahmad1), A. Omar2), A. Mikdad 1)
1) Dept. of Electrical, Electronic and Systems Engineering, Faculty of Engineering, 43600 University Kebangsaan Malaysia,
Malaysia
Phone: 6-03-89296309; fax: 6-03-89296146; e-mail: ibrahim@vlsi.eng.ukm.my, anuar@vlsi.eng.ukm.my,
2) MIMOS Semiconductor (M) Sdn Bhd, MIMOS Berhad, Technology Park Malaysia Kuala Lumpur, Malaysia
Phone: 6-03-89965000; fax: 6-03-89960387; e-mail: abdullah@mimos.my
Abstract. Two doping methods for introducing phosphorus atoms into polysilicon to form a
gate electrode for 0.5 µm CMOS were investigated. These methods were ion implantation and
the �in-situ� one (it is also known as thermal diffusion). For the in-situ method, the concen-
tration of 1.8⋅1020cm�3 for Si2H6
and phosphane (PH3) were used, in the course of ion implan-
tation applying two different doses: 2.0⋅1016 and 3⋅1016cm�2 at 40 keV. The micromorphology
of the polysilicon surface was studied using the atomic force microscopy (AFM). The
polysilicon thickness obtained via the in-situ method ranged between 12.35 and 26.08 nm,
with an average value thickness of 18.0 nm, and its sheet resistance value was 21±1 ohm/square.
As for the ion implantation method, at the lower doses the thickness ranged at about 12.00
upto 46.0 nm with an average value of 24.0 nm, and its sheet resistance values were of 36±13
and 45±21 ohm/square, respectively. At the higher doses, the thickness varied from 12.16 to
47.84 nm with an average meaning 23.96 nm, and its sheet resistance value was between 25 to
40 ohm/square. Therefore, polysilicon doped by the in-situ method has smoother and thinner
surface and possesses better electrical properties.
Keywords: polysilicon gate, micromorphology, ion implantation.
Paper received 12.02.02; revised manuscript received 15.04.02; accepted for publication 25.06.02.
1. Introduction
The gate structure of the CMOS devices has not changed
dramatically in the past several years. The most common
choice of gate materials for modern devices is a layered
structure of polysilicon with metal silicide on top of the
gate. Heavily doped polysilicon films are used to form
the gate conductor in MOSFETs, as a dopant source for
contacts of very shallow junctions in high-speed bipolar
transistors and MOSFETs, as a conductive layer for in-
terconnections, and for electrically trimable resistors. At
a moderate to low dopant concentrations polysilicon is
used for high value resistors and capacitors in analog
designs, and thin-film transistor (TFT) [1,2]. Different
methods of doping and annealing procedures have been
introduced to improve the thermal diffusion process in
order to find the better way in producing the precise dis-
tribution of impurities in which a better electrical char-
acteristics of polysilicon films successfully tailored into
specific application [3]. Ion implantation is another al-
ternative technique of introducing such impurities into
polysilicon with a more precise manner. The dopant atom
is fired into the polysilicon surface through accelerated
ions with energies 20 to 200 keV [4]. Even though the
thermal diffusion is well established for VLSI produc-
tion, the ion implantation offers a few advantages. The
latter provides a better lateral registration of doped re-
gions and superior control of dopant concentration, depth
and uniformity. The fact that repeatability of surface
concentrations of 1016 cm3 or less and uniformity at these
low concentrations is easier to achieve with ion implan-
tation compared to ordinary thermal diffusion process at
high temperature.
In CMOS processes particularly, one of the main rea-
sons for using the polysillicon is due to the fact that
polysilicon allows the integration of �dual-flavoured�
I. Ahmad et al.: The effect of doping methods on electrical properties...
189SQO, 5(2), 2002
gates: p- and n- type polysilicon for PMOS and NMOS,
respectively. Grain sizes and the surface texture of these
films are functions of the polysilicon deposition and dop-
ing conditions as well as subsequent oxidation and ther-
mal cycles [1, 2]. The top surface roughness of the
polysilicon might not be important for the conventional
devices. However, it is of great importance in advanced
three-dimensional (3D) complementary MOS (CMOS),
BiCMOS [3, 4], and for multilevel dielectrics. In these
3D devices, selective epitaxial lateral growth (SEG) and
epitaxial lateral growth (ELG) were used to grow single
crystal silicon on top of the existing polysilicon gates
(polygate) protected by a thermal polyoxide. It is neces-
sary to minimize the roughness of the polysilicon top sur-
face and the roughness of the polyoxide when ELO sili-
con is grown on top of the structure that serves as a sec-
ond MOSFET. In this 3D CMOS structure, the shared
gate is sandwiched between the n-MOS and p-MOS de-
vices. The interface must be smooth to reduce carrier scat-
tering and its state density, as well as potential defect
generation in the ELG silicon [5].
In this work, the micromorphology of the polysilicon
gate for 0.5 mm CMOS devices doped with phosphorous
using both methods aforementioned: the in-situ and ion
implantation are presented. The analysis of the micro-
morphology were afforded by using AFM images which
provide the thickness measure of the polysilicon layer.
The study of electrical properties, namely sheet resist-
ance measurements of the sample, were done using spread
resistance technique.
2. Experimental procedure
The thermal diffusion method for the 0.5 mm CMOS fab-
rication process involves the use of twelve N-type phos-
phorous doped CZ silicon wafers of 100 mm in diameter
and with <100> orientation. First, the wafers were coated
with resist of 1.48 µm thickness. Then, they were devel-
oped in the developing solution for 60 seconds and subse-
quently etched with HF/HNO3. All wafers used were
subjected to a standard RCA cleaning procedure. Next,
a group of four wafers were formed and numbered as wa-
fer 1 to 4, loaded into the vertical furnace for oxide growth
and undergo the thermal drying oxidation process at
900oC for 22 minutes. The four wafers (i.e. wafers no. 1-
4) were then transferred back into the vacuum chamber
for preparation of the 3000oA polysilicon gate electrode
by the low-pressure chemical vapor deposition (LPCVD)
technique using Si2H6 gas with concentration of
1.8⋅1020cm�3 and phosphane (PH3). Next, the other eight
wafers, representing wafer numbers 5 to 12, were depos-
ited with the undoped silicon (3000oA thickness) also by
the LPCVD technique using SiH4 gas instead. Finally,
all wafers are again cleaned with resist of 1.48 µm thick-
ness, followed by backside etching and ashing, to remove
all traces of resist remains at the back of the wafers.
As for the ion implantation method, the wafers are
cleaned with a special chemical called �piranha� before
performing the ion implantation process. This is to re-
move any contaminant and impurities that will contrib-
ute to the formation of long life radioactivity that can
create unwanted contribution to the electrical character-
istics. Next, the wafers were bombarded with 40 keV phos-
phorous ions in an ion implanter. Two wafer sets, con-
sisting of four each, were implanted at different doses of
2.0⋅1016 ions/cm2 (for wafer 5�8) and 3.0⋅1016 ions/cm2
(for wafer 9�12). The choice of doses was based on the
pre-determined estimated data such that it will produce
low conductance polysilicon to agree with the electrical
characteristics shown by the in-situ doping process. The
two-step annealing method was used in this study to ana-
lyse the radiation impacts on the final sheet resistance;
namely, structural and impurities related impacts. The
films was first annealed at 8000C for 30 minutes in dry
nitrogen to repair the structural damage due to ions col-
lisions during implantation. The second annealing step
was done at 9500 C for 5 minutes in dry nitrogen to redis-
tribute the impurities homogeneously throughout the
films. Finally, the wafers were immersed in the buffer
oxide etchant for 30 seconds, rinsed with deionized wa-
ter (DI) and blow dried with dry nitrogen gas to remove
the cap oxide layer.
Sheet resistance measurements were done using four
point probe based instrument of OmniMap Prometrix. It
is a long established technique to measure the average
resistance of a thin layer or a sheet by passing current
through the outside two points of the probe and measur-
ing the voltage across the inside two point [8].
In order to obtain the micromorphology of the
polygate, the atomic force microscopy (AFM) machine
of Digital Instrument Nanoscope III was used and also
subjected to the image enhancing technique to improve
the image resolution [9]. AFM machine, that is capable
of imaging virtually any surface in three dimensions with
scan areas ranging from a few atoms to tens of microns.
The AFM machine was calibrated as mentioned in [10]
prior to the analysis of samples. The instrument was lo-
cated in such a way that it is free from any mechanical,
acoustical and electrical noise or vibration.
The samples were fixed to the stage ensuring that it
does not tilt too much. The suitable load is between
10�8 to 10�9 N and the scanner was set to scan around the
center of the x, y and z axes. The sheet resistance meas-
urement was done using spreading resistance probe (SRP)
of OmniMap Prometrix.
3. Results and discussion
Results obtained are presented in Figs 1 and 2 as well as
summarized in Table 1. Fig. 1 displays the plots of col-
umn pattern over the entire surface and its thickness pro-
file, while Fig. 2 exhibits the relationship between the
sheet resistance and the points of measurement on wafer
obtained from the spread resistance probe (SRP) meas-
urement. The wafer #4 prepared by in-situ doping of
phosphane mixed with silane had sheet resistance value of
around 21±1 ohm/square. The wafer # 11 and # 14 that
190 SQO, 5(2), 2002
I. Ahmad et al.: The effect of doping methods on electrical properties...
Fig. 1. Plots of columns’ patterns over the entire surface of the AFM images with their typical
profiles for the sample No. 4, 11 and 14, respectively.
(a) Sample no. 4
(b) Sample no. 11
(c) Sample no. 14
I. Ahmad et al.: The effect of doping methods on electrical properties...
191SQO, 5(2), 2002
were doped by the implantation method have their sheet
resistance value of 36±13 and 45±21 ohm/square. The
standard deviations of 13 and 21 are very significant val-
ues. These indicate that the variation of the value is too
high and hence, reflect the uncertainties or inconsistence.
The AFM images of the polysilicon wafer of the sam-
ple no. 4 are shown in Fig. 1(a). While the AFM
polysilicon images of samples 11 and 14, implanted by
phosphorus ions, are shown in Fig. 1(b) and 1(c), respec-
tively.
The AFM images of each sample are processed and
analysed to determine the surface micromorphology of
the microstructures. The AFM images are digitally con-
verted and processed using the image processing toolbox
of MATLAB. Image analysis of the microstructure sur-
face of sample 4 indicates that the surface thickness var-
ies from 12.3529 to 26.0784 nm with an average thick-
ness of 18.3962±2.3051 nm. For the sample no. 11, the
thickness varies from 14.3137 to 46.4706 nm with the
average thickness of 24.8613±5.9719 nm, while for the
sample no. 14 the thickness varies from 12.1569 to 47.8432
nm with the average thickness of 23.9502±6.8389 nm
which is rather rough compared to the sample no. 4.
The two steps annealing process were introduced as
means for repairing the radiation damage, and improv-
ing activation by redistributing the impurities. In this
work, using a low temperature furnace, the first anneal-
ing step was able to sweep out point defects while the
subsequent annealing step was able to activate the dopants
[11]. However, we have used higher annealing tempera-
ture since the implantation process was done at higher
energy ion beams.
The polysilicon gate electrode is modeled either as a
perfect conductor or as a heavily doped single-crystal
silicon [12]. We have observed that the electrical con-
ductivity is improved when the grain size is larger, as in
the case of the polysilicon doped by in-situ method. Re-
ferring to Fig. 3 and comparing all three surface micro-
morphology of samples 4, 11 and 14, it is observed that
wafer sample 4 has smoother surface than samples 11
and 14. Thereby, it can be concluded that the sample 4,
which is the thinnest wafer, has better thickness control
compared to samples 11 and 14. In addition, the sample no.
4 has the better value of sheet resistance as shown in Fig.
2.
0
10
20
30
40
50
60
70
1 2 3 4
P o in ts o f m ea su rem en ts a lo n g th e w a fe r
S
h
e
e
t
re
si
st
a
n
ce
,R
s
(O
h
m
/
sq
r.
)
In -situ
2 .0 E1 6 (Im plan t)
3 .0 0E 1 6(Im p la n t)
4. Conclusion
In this work, the influence of doping techniques and im-
purities factors on polysilicon films has been studied us-
ing AFM images. We found that both factors have strong
influence on the electronic properties of the films [13,14].
We have shown that polysilicon doped with phosphane
(PH3) by in-situ produces very thin wafer compared to
samples developed by the ion implantation method. It
can be concluded that polysilicon film doped by the in-
situ method has smoother surface and better thickness
control than the implantation method implying better
electrical conductivity. We also found that the AFM image
analysis is a very useful tool for determining the surface micro-
morphology especially for submicron devices.
Fig. 2. Sheet resistance vs. points of measurements along the
wafer
Sample No. Fabrication method Surface Thickness from AFM Images (nm)
Max Min Average Std. Dev
4 In-situ 26.0784 12.3529 18.3962 2.3051
11 Ion Implantation 46.4706 14.3137 24.8613 5.9719
14 Ion Implantation 47.8432 12.1569 23.9502 6.8389
Table 1. Summary of results from the AFM images
192 SQO, 5(2), 2002
I. Ahmad et al.: The effect of doping methods on electrical properties...
References
1. T. I. Kamins, �Polycrytalline Silicon for Integrated Circuit
Applications�, Kluwer Academic Publishers, 1988.
2. El-Kareh and Badih, �Fundamentals of Semiconductor
Processing Technologies�, Kluwer Academic Publisher,
pp.102-105, 1995.
3. S. M. Sze, �VLSI Technology�, Mc-Graw Hill International,
pp.99-105, 1983.
4. S. M. Sze, �VLSI Technology�, Mc-Graw Hill International,
pp.219-264, 1983.
5. L. Faraone, R.D. Vibronek, and J.T.McGinn, IEEE Trans.
Electron Devices ED-32, 577 (1985)
6. M.T.Duffy, J.T.McGinn, J.M.Shaw, R.T.Smith and R.A.
Soltis, RCA Rev. 44, p. 313 (1983)
7. J.D. Plummer, Michael D. Deal, Peter B. Griffin, �Silicon
VLSI Technology� Prentice Hall, pp 326-328 (2000).
8. S. M. Sze, �Semiconductor Devices�, John Wiley & Sons
Inc., pp 461-466, 2002
9. A. Rosenfeld and A.C. Kak, �Digital Picture Processing�,
Academic Press, 1992
10. M.Suzuki, S. Aoyama, T. Osada, A. Nakano, Y. Sakakibara,
Y. Suzuki, H. Takami, T. Takenobu, M. Yasutuke, J. Vac.
Sci. Tech. A, 14(3), pp. 1228-1232 (1996)
11. A. F. Awang Mat, �Electrical, Structural and Optical Prop-
erties of RF Sputtered and Ion Beam Sputtered Amorphous
Silicon�, PhD. Thesis, J. J. Thompson Physical Laboratory,
University of Reading, 1988.
12. Hillenius S.J., in �Modern Semiconductor Device�, edited
by S.M. Sze, John Wiley, p. 150, 1998
13. T. I. Kamins, M. M. Mandurah, and K.C. Saraswat, J.
Electrochem. Soc. 125, pp.927, 1978.
14. T. I. Kamins, J. Electrochem. Soc. 127, p.686, 1980.
|