Optimal solution in producing 32-nm CMOS technology transistor with desired leakage current
The objective of this paper is to optimize the process parameters of 32-nm CMOS process to get minimum leakage current. Four process parameters were chosen, namely: (i) source-drain implantation, (ii) source-drain compensation implantation, (iii) halo implantation time, and (iv) silicide annealin...
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| Date: | 2011 |
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| Main Authors: | , , , , , , |
| Format: | Article |
| Language: | English |
| Published: |
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
2011
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| Series: | Semiconductor Physics Quantum Electronics & Optoelectronics |
| Online Access: | http://dspace.nbuv.gov.ua/handle/123456789/117716 |
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| Journal Title: | Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| Cite this: | Optimal solution in producing 32-nm CMOS technology transisto with desired leakage current / H.A.Elgomati, I.Ahmad, F.Salehuddin, F.A.Hamid, A.Zaharim, B.Y.Majlis, P.R.Apte // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 145-151 — Бібліогр.: 16 назв. — англ. |