Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs
Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunnelin...
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| Datum: | 2011 |
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| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | English |
| Veröffentlicht: |
Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
2011
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| Schriftenreihe: | Semiconductor Physics Quantum Electronics & Optoelectronics |
| Online Zugang: | http://dspace.nbuv.gov.ua/handle/123456789/117721 |
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| Назва журналу: | Digital Library of Periodicals of National Academy of Sciences of Ukraine |
| Zitieren: | Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ. |