Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

Semiconductor devices with a low gate leakage current are preferred for low power application. As the devices are scaled down, sidewall spacer for CMOS transistor in nano-domain becomes increasingly critical and plays an important role in device performance evaluation. In this work, gate tunnelin...

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Bibliographic Details
Date:2011
Main Authors: Rana, A.K., Chand, N., Kapoor, V.
Format: Article
Language:English
Published: Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2011
Series:Semiconductor Physics Quantum Electronics & Optoelectronics
Online Access:http://dspace.nbuv.gov.ua/handle/123456789/117721
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Journal Title:Digital Library of Periodicals of National Academy of Sciences of Ukraine
Cite this:Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs / Ashwani K. Rana, Narottam Chand, Vinod Kapoor // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2011. — Т. 14, № 2. — С. 203-208. — Бібліогр.: 15 назв. — англ.

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Digital Library of Periodicals of National Academy of Sciences of Ukraine