Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators

Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators

A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0....

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Дата:2006
Автори: Ahmad, Ibrahim, Ho, Yeap Kim, Majlis, Burhanuddin Yeop
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Мова:English
Опубліковано: Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України 2006
Назва видання:Semiconductor Physics Quantum Electronics & Optoelectronics
Онлайн доступ:http://dspace.nbuv.gov.ua/handle/123456789/121430
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Цитувати:Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators / Ibrahim Ahmad, Yeap Kim Ho, Burhanuddin Yeop Majlis // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2006. — Т. 9, № 2. — С. 40-44. — Бібліогр.: 8 назв. — англ.

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spelling irk-123456789-1214302017-06-15T03:04:11Z Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators Ahmad, Ibrahim Ho, Yeap Kim Majlis, Burhanuddin Yeop A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (Vth) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques were implemented: shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped drain implantation, and retrograde well implantation. The results show that drain current (ID) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS were measured. For NMOS, the gate length (Lg) is 0.133 µm, Vth is 0.343138 V, and the gate oxide thickness (Tox) is 3.46138 nm. For PMOS, Lg is 0.133 µm, Vth is −0.378108 V, and Tox is 3.46167 nm. These parameters were validated and the device was proven to be operational. 2006 Article Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators / Ibrahim Ahmad, Yeap Kim Ho, Burhanuddin Yeop Majlis // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2006. — Т. 9, № 2. — С. 40-44. — Бібліогр.: 8 назв. — англ. 1560-8034 PACS 73.40.Qv http://dspace.nbuv.gov.ua/handle/123456789/121430 en Semiconductor Physics Quantum Electronics & Optoelectronics Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
institution Digital Library of Periodicals of National Academy of Sciences of Ukraine
collection DSpace DC
language English
description A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (Vth) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques were implemented: shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped drain implantation, and retrograde well implantation. The results show that drain current (ID) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS were measured. For NMOS, the gate length (Lg) is 0.133 µm, Vth is 0.343138 V, and the gate oxide thickness (Tox) is 3.46138 nm. For PMOS, Lg is 0.133 µm, Vth is −0.378108 V, and Tox is 3.46167 nm. These parameters were validated and the device was proven to be operational.
format Article
author Ahmad, Ibrahim
Ho, Yeap Kim
Majlis, Burhanuddin Yeop
spellingShingle Ahmad, Ibrahim
Ho, Yeap Kim
Majlis, Burhanuddin Yeop
Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators
Semiconductor Physics Quantum Electronics & Optoelectronics
author_facet Ahmad, Ibrahim
Ho, Yeap Kim
Majlis, Burhanuddin Yeop
author_sort Ahmad, Ibrahim
title Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators
title_short Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators
title_full Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators
title_fullStr Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators
title_full_unstemmed Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators
title_sort fabrication and characterization of a 0.14 μm cmos device using athena and atlas simulators
publisher Інститут фізики напівпровідників імені В.Є. Лашкарьова НАН України
publishDate 2006
url http://dspace.nbuv.gov.ua/handle/123456789/121430
citation_txt Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators / Ibrahim Ahmad, Yeap Kim Ho, Burhanuddin Yeop Majlis // Semiconductor Physics Quantum Electronics & Optoelectronics. — 2006. — Т. 9, № 2. — С. 40-44. — Бібліогр.: 8 назв. — англ.
series Semiconductor Physics Quantum Electronics & Optoelectronics
work_keys_str_mv AT ahmadibrahim fabricationandcharacterizationofa014mmcmosdeviceusingathenaandatlassimulators
AT hoyeapkim fabricationandcharacterizationofa014mmcmosdeviceusingathenaandatlassimulators
AT majlisburhanuddinyeop fabricationandcharacterizationofa014mmcmosdeviceusingathenaandatlassimulators
first_indexed 2025-07-08T19:53:11Z
last_indexed 2025-07-08T19:53:11Z
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fulltext Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 2. P. 40-44. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 40 PACS 73.40.Qv Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators Ibrahim Ahmad1, Yeap Kim Ho2, Burhanuddin Yeop Majlis1 1Dept. of Electrical, Electronic and Systems Engineering, Faculty of Engineering 43600 University Kebangsaan Malaysia, MALAYSIA Phone: 6-03-89296309; fax: 6-03-89296146 E-mail: ibrahim@vlsi.eng.ukm.my; burhan@eng.ukm.my 2Dept. of Physical Sciences, Electrical and Electronics, Faculty of Engineering and Science 53300 University Tunku Abdul Rahman, MALAYSIA Phone: 6-03-41079802; fax: 6-03-41079803 E-mail: yeapkh@mail.utar.edu.my Abstract. A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (Vth) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques were implemented: shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped drain implantation, and retrograde well implantation. The results show that drain current (ID) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS were measured. For NMOS, the gate length (Lg) is 0.133 µm, Vth is 0.343138 V, and the gate oxide thickness (Tox) is 3.46138 nm. For PMOS, Lg is 0.133 µm, Vth is −0.378108 V, and Tox is 3.46167 nm. These parameters were validated and the device was proven to be operational. Keywords: gate length, threshold voltage, gate oxide thickness. Manuscript received 19.01.06; accepted for publication 29.03.06. 1. Introduction The size of a CMOS transistor has been shrinking dramatically in less than 40 years time. Transistors with the size of 50 µm in the 1960s have shrunk to less than 0.18 µm in 2000s [1]. In this work, a 0.14 µm CMOS was simulated and studied. The fabrication process was simulated using the ATHENA module from the Silvaco Virtual Wafer Fab (VWF) tools; whereas, the electrical characteristics were validated via the ATLAS module. The 0.14 µm CMOS was scaled from an existing 0.13 µm CMOS [3]. Constant field scaling with a scaling factor of 0.93 was applied to the following parameters: the effective channel length (Lg), gate oxide thickness (Tox), and threshold voltage (Vth) adjustment implantation [5]. As the channel length falls within the submicron regimes, the performance of the device may be susceptible to high field effects. Thus, in order to ensure proper operation, the following techniques have been implemented to minimize high field effects: shallow trench isolation (STI), sidewall spacer deposition, silicide formation, lightly doped drain (LDD) implantation, and retrograde well implantation [5]. 2. Simulation process In order to simplify the simulation process, NMOS and PMOS transistors were fabricated separately. The fabrication processes for both transistors were similar. The main differences lie within the types and density of dopant applied to the substrate. Initially a p-type single crystal silicon (Si) wafer was prepared. Screen oxide was first grown on the Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 2. P. 40-44. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 41 surface of the substrate. With the substrate tilted by 7º and rotating, a high energy implantation was performed to create a p- and n-wells for NMOS and PMOS, respectively. The objective of growing screen oxide and tilting the substrate was to minimize the channeling effect; whereas the objective of rotating the wafer was to minimize the shadowing effect [1]. Annealing and drive- in was later performed to repair the lattice damage [1]. STI is employed to isolate the neighboring devices. Initially, pad oxide is grown via dry oxidation. Liquid plasma chemical vapor deposition (LPCVD) technique is later applied to deposit silicon nitride Si3N4. Pad oxide acts as a strain buffer to avoid cracks in the nitride film; whereas the nitride film acts as a mask for silicon etching [1]. A photoresist is then deposited and pattern is developed using photolithography. The nitride film and pad oxide is etched. The area protected under the Si3N4 mask is known as the active region. After stripping the photoresist layer, the substrate was treated by reactive ion etching (RIE) to form trenches. A thin layer of barrier oxide was grown in the trenches so as to block impurities from diffusing into the substrate during chemical vapor deposition (CVD) process. Then tetra- ethyl-oxy-silane (TEOS) CVD process was applied to fill the trenches with oxide. The oxide at the surface of the substrate was removed using chemical-and- mechanical polishing (CMP) technique. STI was completed after annealing was performed and Si3N4 mask and pad oxide were etched. A thin layer of gate oxide was grown via dry oxidation. Then Vth adjust implantation was performed; after which the substrate was annealed. Subsequently, a layer of polysilicon was deposited on the substrate. Then the substrate was etched and annealed to form a polysilicon gate. LDD was implanted to suppress hot electron effect in submicron MOSFET [1]. After that, CVD was applied to deposit a layer of Si3N4. Then the nitride film was etched to form a sidewall spacer. This was followed by source/drain implantation. Annealing process was performed to activate the dopants. A layer of titanium was deposited on the substrate surface. Rapid thermal annealing (RTA) was employed to form a titanium silicide on the gate. Then the unreacted titanium was etched. Premetal dielectric (PMD) was formed by depositing a layer of boron phosphor silicate glass (BPSG) on the substrate surface. PMD acts as an insulator for multilevel interconnection [2]. After that the annealing is performed, BPSG is etched to form source/drain contacts. The first level of metallization is formed by depositing and etching aluminum on the contacts. The second level of interconnection can be achieved by depositing another layer of BPSG on the surface. This layer is also known as intermetal dielectric (IMD) [2]. The simulation process is completed when Al is deposited onto the contacts formed by etching IMD. A summary of the parameters used in NMOS and PMOS fabrication is shown in Table 1. Table 1. Parameters of CMOS fabrication. Process step NMOS parameters PMOS parameters Silicon substrate • 7.0×1014 cm−3 boron • 〈100〉 orientation • 7.0×1014 cm−3 boron • 〈100〉 orientation Retrograde well implantation • 0.02 µm screen oxide • 3.75×1012 cm−3 boron • 100 keV implant energy • 7º tilt • 30 min, 900 ºC annealing • 36 min, 970 ºC drive-in • 0.02 µm screen oxide • 2.75×1011 cm−3 boron • 100 keV implant energy • 7º tilt • 100 min, 950 ºC annealing • 46 min, 970 ºC drive-in STI isolation • 0.01 µm pad oxide • 0.15 µm Si3N4 • 0.50 µm trench depth • 15 min, 900 ºC annealing • 0.01 µm pad oxide • 0.15 µm Si3N4 • 0.50 µm trench depth • 15 min, 900 ºC annealing Gate oxide • 0.034 µm gate oxide • 0.034 µm gate oxide Vth adjust implantation • 12.45×1011 cm−3 boron • 5 keV implant energy • 12.85×1011 cm−3 boron • 5 keV implant energy Polygate deposition • 0.25 µm polysilicon • 26 min, 850 oC annealing • 0.25 µm polysilicon • 26 min, 850 ºC annealing LDD implantation • 1×1013 cm−3 phosphorous • 23 keV implant energy • 20 min, 800 ºC drive-in • 1×1013 cm−3 boron • 5 keV implant energy • 0.15 min, 850 ºC drive-in Sidewall spacer deposition • 0.12 µm Si3N4 • 0.12 µm Si3N4 Source/drain implantation • 1×1015 cm−3 arsenic • 2×1013 cm−3 phosphorous • 25 keV implant energy • 55 min, 800, 850, 900 ºC annealing • 5×1013 cm−3 boron • 10 keV implant energy • 45 min, 800 ºC annealing Silicide formation • 0.12 µm titanium • 0.02 min, 1100 ºC RTA • 0.1 min, 910 ºC annealing • 0.12 µm titanium • 0.02 min, 1100 ºC RTA • 0.1 min, 910 ºC annealing PMD deposition • 0.30 µm BPSG • 20 min, 850 ºC annealing • 0.30 µm BPSG • 20 min, 850 ºC annealing Metal 1 • 0.10 µm Al • 0.10 µm Al IMD deposition • 0.30 µm BPSG • 15 min, 950 ºC annealing • 0.30 µm BPSG • 15 min, 950 ºC annealing Metal 2 • 0.30 µm Al • 0.30 µm Al Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 2. P. 40-44. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 42 a b Fig. 1. 0.14 µm NMOS (a), PMOS (b). a b Fig. 2. NMOS ID-VD relationship before (a) and after (b) metallization 2. 3. Simulation results and discussions Fig. 1a and b shows the complete cross-sections of NMOS and PMOS, respectively. As clearly shown from the dopant density distributions, a high-energy well implan- tation has resulted in the highest dopant density concent- rated at a certain depth below the substrate surface. As compared to conventional well implantation, in which the highest dopant density lies at the surface of the substrate, such retrograde wells are effective in minimizing punch through. With STI isolation technique implemented in this simulation design, the bird’s beak effect, which is a commonly found problem in local oxidation of silicon (LOCOS) technique, has been successfully eliminated. Two sidewall spacers deposited at the polysilicon gate allows LDD implantation to be performed. As can be seen in Figs 1a and b, the lightly doped phosphorous (for NMOS) and boron (for PMOS) right beneath the spacers allow a reduction in the doping gradient between drain/source and the channel. This, in turn, lowers the electric field at the channel in the vicinity of the drain. A layer of titanium silicide is formed at the surface of the polygate. The layer of silicide, which has much lower resistivity than polysilicon is necessary to reduce power consumptions and RC time delay for submicron MOSFET local interconnection. Some of the important parameters such as Vth, Tox, and Lg are measured and extracted from the ATLAS module. In order to validate the results, these parameters are compared with the standard parameters published by international technology roadmap for semiconductor (ITRS) and Berkeley predictive technology model (BPTM) [4]. Since only the standard parameters for 70 nm, 0.10 µm, 0.13 µm, and 0.18 µm CMOS can be found as published, the polynomial regression technique (using MATLAB tools) has been applied to achieve the required parameters for a 0.14 µm CMOS. Table 2 shows a comparison between the parameters derived from ATLAS and the standard ones obtained using the polynomial regression. All the simulated parameters for Vth, Tox, and Lg lie within the tolerance range of the parameters obtained through regression technique. Hence, it can be concluded that the results obtained from the simulation process are valid. The ID-VD and ID-Vg electrical characteristic curves are plotted using ATLAS simulator. Figs 2a and b show the NMOS ID-VD relationships before and after metallization 2 is performed; whereas, Figs 3a and b show the NMOS ID-Vg relationships before and after metallization 2. Similarly, the ID-VD relationships for PMOS are shown in Figs 4a and b, respectively; whereas, PMOS ID-Vg relationships are shown in Figs 5a and b, respectively. A comparison between before and after second level interconnection is made. The results are summarized in Tables 3 to 6. Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 2. P. 40-44. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 43 a b Fig. 3. NMOS ID-Vg relationship before (a) and after (b) metallization 2. a b Fig. 4. PMOS ID-VD relationship before (a) and after (b) metallization 2. a b Fig. 5. PMOS ID-Vg relationship before (a) and after (b) metallization 2. It can be observed that for both NMOS and PMOS the ID-VD and ID-Vg relationships still retain after the second layer of metallization. This shows that the level of interconnection does not affect the electrical characteristics of the device. However, as the level of interconnection increases, the drain current (ID) increases. Since the power consumption is directly proportional to ID, an increase in the level of interconnection will give rise to power consumption. Semiconductor Physics, Quantum Electronics & Optoelectronics, 2006. V. 9, N 2. P. 40-44. © 2006, V. Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine 44 Table 2. Comparison between simulated results and standard parameters for a 0.14 µm submicron CMOS. CMOS Parameters ATLAS results Standard parameters NMOS Vth 0.343138 V 0.3424 ± 12.7% V Tox 3.46138 nm 3.2158 ± 4% nm Lg 0.133 µm 0.14 ± 15% µm PMOS Vth –0.378108 V –0.3702 ± 12.7% V Tox 3.46167 nm 3.2158 ± 4% nm Lg 0.133 µm 0.14 ± 15% µm Table 3. Comparison of ID before and after metallization 2 in ID-VD NMOS graph. Vg, V VD, V ID before level 2 interconnection, A ID after level 2 intercon- nection, A Rate of increase in ID, % 1.0 0.375 0.00014 0.00015 7.14 2.0 1.0 0.00058 0.00065 12.07 3.0 1.5 0.00100 0.00115 15.00 Table 4. Comparison of ID before and after metallization 2 in ID-Vg NMOS graph. Vg, V VD, V ID before level 2 interconnection, A ID after level 2 Interconnection, A Rate of increase in ID, % 1.5 0.1 0.000075 0.000075 0 1.5 1.1 0.000400 0.000450 12.50 1.5 2.1 0.000430 0.000500 16.28 Table 5. Comparison of ID before and after metallization 2 in ID-VD PMOS graph. Vg, V VD, V ID before level 2 interconnection, A ID after level 2 interconnection, A Rate of increase in ID, % –1.1 –0.75 –0.000150 –0.000150 0 –2.2 –1.5 –0.000413 –0.000450 8.96 –3.3 –2.25 –0.000688 –0.000750 9.01 Table 6. Comparison of ID before and after metallization 2 in ID-Vg PMOS graph. Vg, V VD, V ID before level 2 interconnection, A ID after level 2 interconnection, A Rate of increase in ID, % –1.0 –0.1 –0.000025 –0.000025 0 –1.0 –1.1 –0.000163 –0.000175 7.36 1.0 –2.1 –0.000225 –0.000263 16.89 4. Conclusion With the implement of retrograde well implantation, STI, sidewall spacer deposition, silicide formation, and LDD implantation to help to minimize high field effects, the design of a 0.14 µm submicron CMOS has been successfully simulated and validated. The results show that power consumption tends to increase after the second metallization was performed. References 1. H. Xiao, Introduction to semiconductor manu- facturing technology, Prentice Hall, 2004. 2. M. Quirk and J. Serda, Semiconductor manu- facturing technology, Prentice Hall, 2001. 3. Rosfariza bt. Radzali, Fabrication and charac- terization of a 0.13 micron device, M.Sc. Thesis, University Kebangsaan, Malaysia, 2004. 4. S. Xiong and J. Ding, Impact of parameter variation on future circuit performance, technical report. [Online] Available: http://mechatro2.me.berkeley.edu/ ~jgding/ee241/. 5. C.K. Chen, C.L. Chen, P.M. Gouker, P.W. Wyatt, D.R. Yost, J.A. Burns, V. Suntharalingam, M. Fritze, and C.L. Keast, Fabrication of self-aligned 90 nm fully depleted SOI CMOS SLOTFETs // IEEE Electron Device Lett. 22 (7), p. 345-347 (2001). 6. Y.V. Ponomarev, P.A. Stolk, C.J.J. Dachs, and A.H. Montree, A 0.13 µm poly-SiGe gate CMOS technology for low-voltage mixed signal applications // IEEE Trans. Electron Devices 47 (7), p. 1507-1513 (2000). 7. H. Koike, H. Ohtsuka, F. Matsuoka, M. Kakumu, and K. Maeguchi, Process simplification in deep submicron CMOS fabrication // IEEE/UCS/SEMI International Symposium Semiconductor Manufacturing, 24-27 (1995). 8. D. Parent, E. Basham, Y. Dessouky, S. Gleixner, G. Young, E. Allen, Improvements to a microelectronic design and fabrication course // IEEE Trans. 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